___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 1 mk - qb -p-d-120917- 01 -2 crystal-less two output pcie gen1/2/3 clock generator dsc 557 - 03 general description the dsc 557 - 03 is a crystal-less, two output pci express clock generator meeting gen1, gen2, and gen3 specifications. the clock generator uses proven silicon mems technology to provide 100mhz* differential output clocks with excellent jitter and stability over a wide range of supply voltages and temperatures. by eliminating the external quartz crystal, the dssc557- 03 significantly enhances reliability and accelerates product development, while meeting stringent clock performance criteria for a variety of communications, storage, and networking applications. dsc557-03 has an output enable / disable feature allowing it to disable the outputs when oe is low. the device is available in two different packages; a drop - in replacement 16 pin tssop or a space saving 14 pin qfn (77% less board space) . additional output formats are also available in any combination of lvpecl, lvds, and hcsl. block diagram control circuitry mems pll output control and divider clk1+ clk1- clk0+ clk0- oe * clk0+/- and clk1+/- are 100 mhz as per pcie standards. for other frequencies, please contact the factory. features ? meets pcie gen1, gen2 & gen3 specs. ? available output formats: o hcsl, lvpecl, or lv ds o hcsl/lvpecl, hcsl/lvds, lvpecl/lvds ? wide temperature range o ext. industrial: -40 to 105 c o industrial: -40 to 85 c o ext. commercial: -20 to 70 c ? supply range of 2.25 to 3.6 v ? low power consumption o 30% lower than competing devices ? excellent shock & vibration immunity o qualified to mil-std- 883 ? available footprints: o 16 tssop o 14 qfn ? lead free & rohs compliant ? short lead time: 2 weeks applications ? communications/networking o ethernet o 1g, 10gbase-t/kr/lr/sr, and fcoe o routers and switches o gateways, voip, wireless aps o passive optical networks ? storage o san, nas, ssd, jbod ? embedded applications o industrial, medical, and avionics o security systems and office automation o digital sinage, pos and others ? consumer electronics o smart tv, bluray, stb downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 2 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator specifications (unless specified otherwise: t=25 c, vdd =3.3v) notes: 1. v dd should be filtered with 0.01uf capacitor. 2. output is enabled if oe pin is floated or not connected. 3. t su is time to 100ppm stable output frequency after v dd is applied and outputs are enabled. 4. output waveform and connection diagram define the paramet ers. 5. period jitter includes crosstalk from adjacent output. 6. contact sales@discera.com for alternate output options (lvpecl, lvds, lvcmos). 7. contact sales@discera.com for alternative frequency options 8. jitter limits established by gen 1.1, gen 2.1, and gen 3.0 pci e standards. parameter condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current i dd en pin low C outputs are disabled 21 23 ma supply current 2 (two hcsl outputs) i dd en pin high C outputs are enabled r l = 50 , f o1 =f o2 =100 mhz 60 ma frequency stability f includes frequency variations due to initial tolerance, temp. and power supply voltage 100 ppm 50 startup time 3 t su 5 ms input logic levels input logic high input logic low v ih v il 0.75xv dd - - 0.25xv dd v output disable time 4 t da 5 ns output enable time t en 20 ns pull-up resistor 2 pull-up on oe pin 40 k hcsl outputs 6 parameter condition min. typ. max. unit output logic levels output logic high output logic low v oh v ol r l =50 0.725 - - 0.1 v pk to pk output swing single-ended 750 mv output transition time 4 rise time fall time t r t f 20% to 80% r l =50 , c l = 2pf 200 400 ps frequency f 0 single frequency 2.3 100 7 4 60 mhz output duty cycle sym differential 48 52 % period jitter 5 j per f o1 =f o2 =100 mhz 2. 5 ps rms jitter, phase (common clock architecture) r j pcie gen 1.1 t j =d j + 14.069 x r j (ber 10- 12) 0.540 ps rms d j t j pcie gen 1.1 t j =d j + 14.069 x r j (ber 10- 12) 0.832 8.536 41.9 8 86.0 8 ps p-p j rms-cchf pcie gen 2.1, 1.5 mhz to nyquist 0.458 3.1 8 ps rms j rms- cclf pcie gen 2.1, 10 khz to 1.5 mhz 0.030 3.0 8 ps rms j rms- cc pcie gen 3.0 0.165 1.0 8 ps rms integrated phase noise (data clock architecture) j rms-dchf pcie gen 2.1, 1.5 mhz to nyquist 0.561 4.0 8 ps rms j rms-dclf pcie gen 2.1, 10 khz to 1.5 mhz 1.778 7.5 8 ps rms j rms- dc pcie gen 3.0 0.147 1.0 8 ps rms downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 3 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator absolute maximum ratings item min max unit condition supply voltage -0.3 +4.0 v input voltage -0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40sec max. esd hbm mm cdm - 4000 400 1500 v solder reflow profile 14 qfn msl 1 @ 260c refer to jstd-020c 16 tssop msl 3 @ 260c refer to jstd-020c ramp-up rate (200c to peak temp) 3c/sec max. preheat time 150c to 200c 60 - 180 sec time maintained above 217c 60 -150 sec peak temperature 255 - 260 c time within 5c of actual peak 20 -40 sec ramp-down rate 6c/sec max. time 25c to peak temperature 8 min max. 60 -150 sec 20 - 40 sec 60 -180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60 -150 sec 20 - 40 sec 60 -180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60 -150 sec 20 - 40 sec 60 -180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 4 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator pin diagram (16 tssop) connection diagram (16 tssop two hcsl outputs) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc oe vss nc nc clk1+ clk1- nc nc clk0- clk0+ vdd 16-tssop (173 mil) (5.1 x 6.8 mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + vdd - + enable - 0.01 uf 50 w 50 w 50 w 50 w clk1+ clk1- clk0+ clk0- ropt ropt 22 w - 33 w optional pin description (16 tssop) pin no. pin name 9 pin type description 1 nc na no connect 2 nc na no connect 3 nc na no connect 4 nc na no connect 5 nc na no connect 6 oe i output enable; active high 7 vss power ground 8 nc na no connect 9 nc na no connect 10 clk1+ o t rue output of differential pair 11 clk1- o complement output of differential pair 12 nc na no connect 13 nc na no connect 14 clk0- o complement output of differential pair 15 clk0+ o t rue output of differential pair 16 vdd power power supply downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 5 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator pin diagram (14 qfn) connection diagram (14 qfn two hcsl outputs) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc nc nc oe vss nc clk1+ clk1- clk0- clk0+ vdd1 14 qfn 3.2x2.5mm nc nc vdd0 + vdd - + enable - 0.01 uf 50 w 50 w 50 w 50 w clk1+ clk1- clk0+ clk0- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.01 uf ropt ropt 22 w - 33 w optional pin description (14 qfn) pin no. pin name pin type description 1 oe i output enable; active high 2 nc na ground recommended or leave as a nc 3 nc na ground recommended or leave as a nc 4 vss power ground 5 nc na ground recommended or leave as a nc 6 nc na ground recommended or leave as a nc 7 nc na ground recommended or leave as a nc 8 clk1+ o t rue output of differential pair 9 clk1- o complement output of differential pair 10 clk0- o complement output of differential pair 11 clk0+ o t rue output of differential pair 12 vdd 1 power power supply for core and output 1 (clk0+/-) 13 vdd0 power power supply for output 0 (clk1+/-) 14 nc na ground recommended or leave as a nc downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 6 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator oe function and output waveform: hcsl ordering information 9 note 9 . clk0 and clk1 are configured at the factory to 100 m hz. (for other frequencies, contact the factory at sales@discera.com.) v il 1/ f o output enable t da t en t f t r v ih 80 % 20% 50% output 830 mv dsc557- 03 packing t: tape & reel f i 0 package f: 14 qfn s: 16 tssop temp range e: -20 to 70 i: -40 to 85 l: -40 to 105 stability 0: 100ppm 1: 50ppm t clk 1 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl 4 4 - clk 0 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl 675 mv downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 7 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator package dimensions f: 14 qfn , 3.2 x 2.5 mm downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 8 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator s: 16 tssop (173 mil body width) recommended solder pad layout units mm [in] 0.65 [0.256] 0.3 [0.012] 4.6 [0.181] 6.8[0.268] 1.1[0.043] 4.85 [0.191] downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc557- 03 page 9 mk - qb -p-d-120917- 01 -2 dsc557-03 crystal-less two output pcie gen1/2/3 clock generator disclaimer: micrel makes no representations or warranties with respec t to the accuracy or completeness of the information fu rnished in this data sheet. this information is not intended as a warranty and micrel does not assum e responsibility for its use. micrel reserves the right t o change circuitry, specifications and descriptions at any time without notice. no license, wheth er express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrel s terms and conditions of sale for such products, micrel a ssumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or us e of micrel products including liability or warranties relating t o fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. micrel products are not designed or authorized for use a s components in life support appliances, devices or syste ms where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably ex pected to result in a significant injury to the user. a pu rchasers use or sale of micrel products for use in life support appliances , devices or systems is a purchasers own risk and pu rchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. micrel, inc. 2180 fortune drive, san jose, california 95131 usa phone: +1 (408) 944-0800 fax: +1 (408) 474 -1000 email: hbwhelp@micrel.com www.micrel.com downloaded from: http:///
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